The present invention relates to an interface for a semiconductor integrated circuit.
In recent years, as the number of semiconductor large-scale integrated circuits (hereinafter, simply referred to as "LSI's"), integrated on a single chip, and the operating speed thereof have been tremendously increased, the power dissipation has also increased noticeably. In order to suppress such increase in power consumption, LSI's are often operated with a reduced power supply voltage. However, it is not always possible to operate all LSI's , included in a single circuit, with an equally reduced power supply voltage. If not, interfacing an LSI operating at a relatively high power supply voltage (e.g., 5 V) with another LSI operating at a relatively low power supply voltage (e.g., 3.3 V) plays an important role in suppressing such unwanted increase in power consumed. Nevertheless, connection of an input/output terminal of an LSI operating at a relatively high voltage like 5 V to that of another LSI operating at a relatively low voltage like 3.3 V causes the following two problems.
First, if the LSI operating at 3.3 V receives a voltage (e.g., 5 V) higher than the power supply voltage thereof (i.e., 3.3 V), then a p-channel MOS transistor, implemented as an output circuit section of an input/output circuit, turns ON. In such a case, current is unintentionally passed from an input/output terminal through the p-channel MOS transistor into a power line inside the LSI. Since the input/output terminal should have high impedance during input operation, such unwanted current supply increases power consumption unnecessarily.
Second, the gate oxide film of an MOS transistor inside the LSI operating at 3.3 V often has a breakdown voltage no higher than the power supply voltage thereof (i.e., 3.3 V). Accordingly, if a high voltage such as 5 V is applied to the film, then dielectric breakdown happens in the MOS transistor, because the applied voltage exceeds the breakdown voltage of the gate oxide film.
Means for solving these problems are disclosed, for example, in U.S. Pat. No. 5,555,149.
Hereinafter, the prior art input/output circuit described in the above-identified patent will be described with reference to the accompanying drawings. It should be noted that the input/output circuit can solve these two problems.
FIG. 3 illustrates the configuration of the prior art input/output circuit.
As shown in FIG. 3, the input/output circuit includes: an input/output terminal IO; an input terminal IN; an output terminal OUT; an enable terminal EN; an output circuit 1; and an input circuit 2. The input/output terminal IO is used for exchanging signals with external circuits outside of an LSI. At the input terminal IN, signals are received from other circuits inside the LSI. Conversely, through the output terminal OUT, signals are output to other circuits inside the LSI. And the enable terminal EN is used for switching the output/input states of the input/output terminal IO.
In the output circuit 1, if the enable terminal EN is at a high, or "H", level, a signal, received at the input terminal IN, is output through the input/output terminal IO. Alternatively, if the enable terminal EN is at a low, or "L", level, the input/output terminal IO comes to have high impedance.
The output circuit 1 further includes: p-channel MOS (PMOS) transistors 11, 12 and 13; n-channel MOS (NMOS) transistors 14, 15, 16 and 17; an inverter 18; a NAND circuit 19; a NOR circuit 20; a power supply terminal 21; and a ground terminal 22. The PMOS transistors 11 and 12 are serially connected between the power supply terminal 21 and the input/output terminal IO. The NMOS transistors 14 and 15 are serially connected between the input/output terminal IO and the ground terminal 22.
The output of the NAND circuit 19 is supplied to the gate of the PMOS transistor 11, to the gate of the PMOS transistor 12 through the serially connected NMOS transistors 17 and 16, and to the gate of the NMOS transistor 17 via the inverter 18. One of the input terminals of the NAND circuit 19 is connected to the enable terminal EN, while the other terminal thereof is connected to the input terminal IN. The input/output terminal IO and the gate of the PMOS transistor 12 are connected to each other via the PMOS transistor 13. The respective gates of the PMOS and NMOS transistors 13, 14 and 16 are connected to the power supply terminal 21.
The output of the NOR circuit 20 is supplied to the gate of the NMOS transistor 15. One of the input terminals of the NOR circuit 20 receives an inverted signal of the signal received at the enable terminal EN, while the other terminal thereof is connected to the input terminal IN.
The input circuit 2 receives a signal supplied from the input/output terminal IO and outputs the signal through the output terminal OUT to other circuits inside the LSI.
The operation of the input/output circuit having such a configuration will be described in terms of the operation of outputting a signal, supplied from internal circuits in the output circuit 1, through the input/output terminal IO, in particular.
In outputting a signal through the input/output terminal IO, the enable terminal EN should be at "H" level.
First, the operation of outputting an "H" level signal, received at the input terminal IN, through the input/output terminal IO will be described. In this case, the respective outputs of the NAND and NOR circuits 19 and 20 are both at "L" level. Since the respective gates of the PMOS and NMOS transistors 13, 14 and 16 are connected to the power supply terminal 21, an "H" level signal is always supplied to these gates. Accordingly, the PMOS transistor 13 turns OFF, while the NMOS transistors 14 and 16 turn ON. In response to the "L" level signal supplied from the NAND circuit 19, the inverter 18 outputs an "H" level signal, thereby turning the NMOS transistor 17 ON. In this case, the respective gates of the PMOS and NMOS transistors 11, 12 and 15 are all at "L" level. Accordingly, the PMOS transistors 11 and 12 turn ON, while the NMOS transistor 15 turns OFF. As a result, the "H" level signal, supplied from the power supply terminal 21, is output through the input/output terminal IO via the PMOS transistors 11 and 12.
Next, the operation of outputting an "L" level signal, received at the input terminal IN, through the input/output terminal IO will be described. In this case, the respective outputs of the NAND and NOR circuits 19 and 20 are both at "H" level. Since the respective gates of the PMOS and NMOS transistors 13, 14 and 16 are connected to the power supply terminal 21, an "H" level signal is always supplied to these gates. Accordingly, the PMOS transistor 13 turns OFF, while the NMOS transistors 14 and 16 turn ON. In response to the "H"0 level signal supplied from the NAND circuit 19, the inverter 18 outputs an "L" level signal, thereby turning the NMOS transistor 17 OFF. In this case, since the "H" level signal is supplied to the gate of the PMOS transistor 13 to turn the transistor 13 OFF, the gate voltage at the PMOS transistor 12 is indefinite. Also, since the respective gates of the PMOS and NMOS transistors 11 and 15 are both at "H" level, the PMOS transistor 11 turns OFF, while the NMOS transistor 15 turns ON. Similarly, the NMOS transistor 14 has also received the "H" level signal at the gate thereof and is ON. As a result, the "L" level signal, supplied from the ground terminal 22, is output through the input/output terminal IO via the NMOS transistors 15 and 14.
Although the state of the PMOS transistor 12 is indefinite, no current flows from the power supply terminal 21 to the input/output terminal IO, because the PMOS transistor 11, serially connected to this transistor 12, is OFF.
Next, the operation of inputting a signal, received at the input/output terminal IO, to other internal circuits inside the LSI will be described.
In inputting the signal, received at the input/output terminal IO, to other internal circuits, the enable terminal EN should be at "L" level. In such a case, the output circuit 1 has high impedance with respect to the input/output terminal IO. Hereinafter, the operation of the output circuit 1 in the high-impedance state will be described.
If the enable terminal EN is at "L" level, then the output of the NAND circuit 19 is at "H" level, while the output of the NOR circuit 20 is at "L" level. The "H" and "L" level signals are supplied to the gates of the PMOS and NMOS transistors 11 and 15, respectively. As a result, these transistors 11 and 15 both turn OFF. Accordingly, no current path is available from the input/output terminal IO. In other words, if the PMOS and NMOS transistors 11 and 15 are OFF, there is no current path connecting the power supply or ground terminal 21 or 22 to the input/output terminal IO. In such a case, the output circuit 1 has high impedance.
If a signal is received at the input/output terminal IO in such a state, then the signal is passed through the input circuit 2 and output through the output terminal OUT to other internal circuits.
Hereinafter, it will be described how the output circuit 1 operates if a voltage, higher than a power supply voltage, is applied through the input/output terminal IO. In the following example, the power supply voltage at the power supply terminal 21 is supposed to be 3.3 V and a voltage (e.g.,5 V), higher than the power supply voltage, is supposed to be applied through the input/output terminal IO.
Since a voltage at one terminal (i.e., 5 V) of the PMOS transistor 13 is higher than the gate voltage thereof (i.e., 3.3 V), the PMOS transistor 13 turns ON. And the input signal (5 V), received at the input/output terminal IO, is transmitted to the gate of the PMOS transistor 12. In response to this signal, the gate voltage of the PMOS transistor 12 increases to 5 V, and the PMOS transistor 12 turns OFF. Accordingly, the current path from the input/output terminal IO to the power supply terminal 21 is blocked.
The signal (5 V), received at the input/output terminal IO, is also transmitted to the NMOS transistor 16. However, since the gate voltage (3.3 V) at the NMOS transistor 16 is equal to or lower than the voltage (5 V) at one terminal thereof or the voltage (3.3 V) at the other terminal thereof, the NMOS transistor 16 turns OFF. Accordingly, the input signal (5 V), transmitted from the input/output terminal IO through the PMOS transistor 13 to the NMOS transistor 16, is not passed to the NMOS transistor 17.
Moreover, since the NMOS transistor 15 is also OFF, no current flows from the input/output terminal IO to the ground terminal 22, either.
Furthermore, although 5 V is applied to one terminal of the NMOS transistor 14 and one terminal of the NMOS transistor 16, only a potential difference between 5 and 3.3 V, i.e., 1.7 V, is applied to the gate oxide film thereof, because the gate voltage thereof is 3.3 V. Accordingly, no breakdown happens in the gate oxide film. Similarly, although 5 V is applied to both terminals of the PMOS transistor 13, only a potential difference between 5 and 3.3 V, i.e., 1.7 V, is applied to the gate oxide film thereof, because the gate voltage thereof is also 3.3 V. Thus, no breakdown happens in the gate oxide film, either. Although 5 V is applied to the gate of the PMOS transistor 12, the voltage at the gate oxide film thereof is also 1.7 V, because one terminal of the PMOS transistor 12 receives 5 V and the other terminal thereof receives 3.3 V. The voltage at the other terminal of the NMOS transistor 14 is a voltage obtained by subtracting the threshold voltage of the NMOS transistor 14 (defined at 1 V considering back bias effect) from the gate voltage thereof (3.3 V), i.e., 2.3 V. Thus, this voltage does not have harmful effect on the NMOS transistor 15.
In the output circuit 1 of this input/output circuit shown in FIG. 3, to output the "H" level signal, received at the input terminal IN, through the input/output terminal IO, the signal has to pass through NAND circuit 19, inverter 18, NMOS and PMOS transistors 17, 16 and 12 and terminal IO. Accordingly, a very long delay is involved between the input of the signal to the input terminal IN and the output thereof from the input/output terminal IO.
In the context of semiconductor integrated circuit technology, a power supply voltage is reduced for the purpose of suppressing increase in power dissipation when a greater number of LSI's are integrated or when the operating speed of each LSI is increased. Accordingly, such a prolonged delay is contrary to this very purpose and therefore unacceptable.
In addition, the NAND circuit 19 should drive the inverter 18, NMOS transistors 17 and 16 and PMOS transistors 11, 12 and 13. If these inverter and transistors are to be driven at a higher speed, then the size of the transistor constituting the NAND circuit 19 should be increased, which is contradictory to the missions of increasing the number of LSI's integrated and reducing power consumption.